“From a 3-speed bike to a 20-speed bike” – Scientists move closer to new technology that combines ultra-expensive but super-fast SRAM and DRAM
- Stanford scientists want to combine SRAM and DRAM
- The new memory type would help solve problems with AI computing
- Gain Cell memory seems to bridge the gap between the two types
The development of more energy-efficient hardware for artificial intelligence (AI) systems is gaining support, with a focus on improving memory technology.
A hybrid type of memory that combines the high density of DRAM (Dynamic Random-Access Memory) with the speed of SRAM (Static Random-Access Memory) is at the forefront of this effort.
The project is led by electrical engineers from Stanford University, with the goal of creating faster, more efficient memory hardware for AI applications that addresses current limitations in processing power and energy consumption.
Memory, a major AI bottleneck – hybrid cell memory amplification comes to the rescue
This research is funded under the CHIPS and Science Act, with a recent boost of $16.3 million in funding from the U.S. Department of Defense to the California-Pacific-Northwest AI Hardware Hub.
AI systems rely heavily on hardware that can move and process large amounts of data efficiently. However, moving data between memory and logic takes time, which slows down GPUs and leads to higher power consumption.
As AI models become larger and more complex, these memory bottlenecks become increasingly apparent. Therefore, faster and more compact memory located directly on chips is seen as a possible solution to this problem.
H.-S. Philip Wong, electrical engineer and president of the AI Hardware Hub, emphasizes the importance of memory in making AI hardware more energy efficient.
Wong’s team has turned to a new type of memory design called Gain Cell memory, which combines the benefits of both DRAM and SRAM. The hybrid gain cell offers a middle ground that has the small footprint of DRAM, but also offers the faster readout speeds typical of SRAM.
The main difference in this new design is the use of two transistors: one for writing data and one for reading instead of the capacitor found in traditional DRAM. This allows the gain cell to retain data more reliably and boost signal strength when data is read.
Gain cell memory has faced limitations such as fast data leakage in silicon-based designs and slower readout speeds in oxide-based designs. However, the Stanford team combined a silicon transistor with an indium tin oxide transistor, significantly improving the device’s performance and allowing faster readouts while maintaining a compact footprint.
The new design can retain data for over 5,000 seconds, much longer than traditional DRAM, which must be refreshed every 64 milliseconds. In addition, the hybrid memory is approximately 50 times faster than oxide-oxide booster cells.
Wong compares this advancement to moving from a standard 3-speed bike to an advanced 20-speed bike, emphasizing that this evolution of memory technology will go beyond traditional options such as DRAM, SRAM and flash memory. “We want to provide better options so that designers can optimize better. It’s an opportunity to redesign computers,” said Wong.
Via IEEE
